Integrated circuits form an essential part of modern electronic equipment. There is an increasing reliance on portable equipment with intensive processing requirements and limited battery life. In view of this, there is considerable interest in a logic style, which offers low power consumption.
Some logic styles are based on decreasing the swing of the signal (reduced swing technique) so as to reduce power consumption.
One of such logic styles is the Short Circuit Current Logic (SCL) as described by Fahim A. M. et Elmasry M. I. in “Low power high performance arithmetic circuits and architectures”, JSSC, volume 37, January 2002. In SCL, the limited discharge is partly realised by a short-circuit current of an inverter. The output swing is thus a function of the inverter sizing, but also of the slope of the clock signal.
Another logic, called Clock-Pulse Control Logic (CPCL), uses a pulse to produce a partial discharge of the outputs. This pulse is realised at the start of the leading edge of the clock signal and by a high-pass circuit of the RC type. However, this logic shows a high sensitivity with respect to the value of the load capacitance. This leads to constraints on the sizing of some transistors in the circuit.
The MOS Current Mode Logic (MCML) is a type of logic operation with low swing. It is implemented with a differential pair. The value of input variables controls the current in the two differential branches. This type of logic is described by M. Yamashina and al., in “MOS current mode logic MCML circuit for low power GHz processors”, NEC Res. Develop., vol. 36, no. 1, pp. 54-63, January 1995.